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  pfc-coolset ICE1PD265G ic for high power factor and low thd never stop thinking. datasheet, v1.0, 10 sep 2001 power management & supply
edition 2001-09-10 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen ? infineon technologies ag 1999. all rights reserved. attention please! the information herein is given to describe certain com ponents and shall not be considered as warranted charac- teristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warrant ies, including but not limited to warran ties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and co nditions and prices please contact your nearest infi- neon technologies office in germany or our infineon tec hnologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or system s with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representat ives worldwide: see our webpage at http:// www.infineon.com coolmos?, coolset? are trademarks of infineon technologies ag. ccm-pfc revision history: 2001-09-10 datasheet previous version: v1.0
ICE1PD265G version 1.0 3 10 sep 2001 gnd ac rf-filter and rectifier dc output voltage ice 1pd265g coolmos controller power factor controller + cool- mos: boostset ic for high power factor and low thd ?= ic for sinusoidal line-current consumption ?= controller and coolmos within one package ?= p-dso-16-10 ?= power factor achieves nearly 1 ?= controls boost converter as active harmonic filter for low thd ? start up with very low current consumption ?= zero current detector for discontinuous opera- tion mode ? output overvoltage protection ?= output undervoltage lockout ?= internal start up timer ?= totem pole output with active shut down ?= internal leading edge blanking leb ?= very low comparator and multiplier offsets for universal input applications ?= high sophisticated amplifier minimizes distor- tion inteferences caused by mosfet switching the ICE1PD265G ic controls a boost converter in a way that sinusoidal current is taken from the single phase line supply and stabilized dc voltage is available at the output. coolmos and controller are placed together in one package. this active harmonic filter limits the harmonic currents resulting from the capacitor pulsed charge currents during rectification. the power factor which descibes the ratio between active and apparent power is almost one. line voltage fluctuations can be compensated very effi- ciently type ordering code package ICE1PD265G p-dso-16-10
ICE1PD265G version 1.0 4 10 sep 2001 pin connections pin description pin1,16 gnd (ground) the gnd pins are internally connected via the lead frame pin 2 vsense (voltage amplifier inverting input) vsense is connected via a resistive divider to the boost converter output. with a capacitor connected to vaout the internal error amplifier acts as an integrator. pin 3 vaout (voltage amplifier output) vaout is connected internally to the first multiplier input. to prevent overshoot the input voltage is clamped internally at 5v. input voltage less then 2.2v shuts the gate driver down. if the current flowing into this pin is exceeding an internal threshold the multiplier output voltage is reduced to prevent the mosfet from overvoltage damage. pin 4 multin (multipier input) multin is the second multiplier input and is connected via a resistive divider to the rectifier output voltage. pin 5, 12 not connected pin 6,7,8,9,10,11 drain (drain connection of internal coolmos) the drain pins are internally connected via the leadframe. be aware of 650v input voltage! pin symbol function 1 gnd ground 2 vsense voltage amplifier inverting input 3 vaout voltage amplifier output 4 multin multiplier input 5n.c. 6 drain 650v drain 7 drain 650v drain 8 drain 650v drain 9 drain 650v drain 10 drain 650v drain 11 drain 650v drain 12 n.c. 13 isense current sense input + source 14 vcc positive voltage supply 15 detin zero current detector input 16 gnd ground 1 gnd 2 vsense 3 vaout 4 multin 16 gnd 15 detin 14 vcc 13 isense 6 drain 7 drain 8 drain 9 drain 10 drain 11 drain p-dso-16-10 5 n.c. 12 n.c. do not touch drain pins on application board: 650v
ICE1PD265G version 1.0 5 10 sep 2001 0.2v reference voltage gate drive + - voltage amp multiplier rs flip-flop + - uvlo leb restart timer + - detector vsense vaout multin isense detin vcc gnd + - current comp multout + + - - inhibit time delay 2.2v 2.5v uvlo active shut down 1.5 v 1.0 v 12.5v 10v t dva =2us t res =150 us t leb =150ns t dsd =70n s 20v clamp va clamp detin + 1v inhibit enable ovr cool mos drain 20k 10p 10 pin 13 isense (current sense input and coolmos source) controller current sense input and coolmos source are internaly connected via bonds. isense should be connected to an external sense resistor controlling the coolmos source current. the input is internally clamped at -0.3v to prevent negative input voltage interaction. a leading edge blanking circuitry suppresses voltage spiks when turning the mosfet on. pin 14 vcc (positive voltage supply) if vcc exceeds the turn-on threshold the ic is switched on. when vcc falls below the turn-off threshold it is switched off and power consumption is very low. an auxilliary winding is charging a capacitor which provides the supply current. a second 100nf ceramic capacitor should be added to vcc to absorbe supply current spikes required to charge the mosfet gate capacitance. pin 15 detin (zero current detector input) detin is connected to an auxiliary winding monitoring the zero crossing of the inductor current. block diagram
ICE1PD265G version 1.0 6 10 sep 2001 functional description introduction conventional electronic ballasts and switching power supplies are designed with a bridge rectifier and a bulk capacitor. their disadvantage is that the circuit draws power from the line when the instantaneous ac voltage exceeds the capacitors voltage. this occurs near the line voltage peak and causes a high charge current spike with following characteristics: the apparent power is higher than the real power that means low power factor condition, the current spikes are non sinusoidal with a high content of harmonics causing line noise, the rectified voltage depends on load condition and requires a large bulk capacitor, special efforts in noise suppression are necessary. with the ICE1PD265G preconverter a sinusoidal current is achieved which varies in direct instanta- neous proportional to the input voltage half sine wave and so provides a power factor near 1. this is due to the appearence of almost any complex load like a resistive one at the ac line. the harmonic distortions are reduced and comply with the iec555 standard requirements. ic description the ICE1PD265G contains a wide bandwidth voltage amplifier used in a feedback loop, an overvolt- age regulator, an one quadrant multiplier with a wide linear operating range, a current sense compa- rator, a zero current detector, a pwm and logic circuitry, a totem-pole mosfet driver, an internal trimmed voltage reference, a restart timer, an undervoltage lockout circuitry and last not least a coolmos transistor. voltage amplifier with an external capacitor between vsense and vaout the voltage amplifier forms an integrator. the integrator monitors the average output voltage over several line cycles. typically the integrators bandwidth is set below 20 hz in order to suppress the 100 hz ripple of the rectified line voltage. the voltage amplifier is internally compensated and has a gain bandwidth of 3 mhz and a phase margin of 80 degrees. the non-inverting input is biased internally at 2.5v. the output is directly connected to the multiplier input. the gate drive is disabled when vsense voltage is less than 0.2 v or vaout voltage is less than 2.2 v. if the mosfet is placed nearby the controller switching inteferences have to be taken into account. the output of the voltage amplifier is designed in a way to minimize these inteferences. overvoltage regulator because of the integrators low bandwidth fast changes of the output voltage can?t be regulated whithin an adequate time. fast output changes occure during initial start-up, sudden load removal, or output arcing. while the integrators differential input voltage remains zero during this fast changes a peak current is flowing through the external capacitor into pin vaout. if this current exceeds an internal defined margin the overvoltage regulator circuitry reduces the multiplier output voltage. as a result the on time of the mosfet is reduced.
ICE1PD265G version 1.0 7 10 sep 2001 multiplier the one quadrant multiplier regulates the gate driver with respect of the dc output voltage and the ac half wave rectified input voltage. both inputs are designed to achieve good linearity over a wide dynamic range to represent an ac line free from distortion. special efforts are made to assure uni- versal line applications with respect to a 90 to 270 v ac range. the multiplier output is internally clamped at 1.0v. so the mosfet is protected against critical operating during start up. current sense comparator, leb and rs flip-flop an external sense resistor transferes the source current of the mosfet into a sense voltage.the multiplier output voltage is compared with this sense voltage. to protect the current comparator input from negative pulses a current source is inserted which sends current out of the isense pin every time when isense is falling below ground potential. the switch-on current peak of the mosfet is blanked out via a resistor-capacitor circuit with a blanking time of typically 220ns. therefore better thd is achieved at low load conditions. the rs flip-flop ensures that only one single switch-on and switch-off pulse appears at the gate drive output during a given cycle (double pulse suppression). zero current detector the zero current detector senses the inductor current via an auxiliary winding and ensures that the next on-time of the mosfet is initiated immediately when the inductor current has reached zero. this diminishes the revers recovery losses of the boost converter diode. the mosfet is switched off when the voltage drop of the shunt resistor reaches the voltage level of the multipler output. so the boost current waveform has a triangular shape and there are no deadtime gaps between the cycles. this leads to a continuous ac line current limiting the peak current to twice of the average current. to prevent false tripping the zero current detector is designed as a schmitt-trigger with a hysteresis of 0.5v. an internal 5v clamp protects the input from overvoltage breadkdown, a 0.6v clamp pre- vents substrate injection. an external resistor has to be used in series with the auxiliary winding to limit the current through the clamps. restart timer if the mos is off for more than 150us a restart impulse is generated by the restart timer.
ICE1PD265G version 1.0 8 10 s ep 2001 undervoltage lockout an undervoltage lockout circuitry switches the ic on when vcc reaches the upper threshold v cch and switches the ic off when vcc is falling below the lower threshold v ccl . during start up the sup- ply current is less then 100ua. an internal voltage clamp has been added to protect the ic from vcc overvoltage condition. when using this clamp special care must be taken on power dissipation. start up current is provided by an external start up resistor which is connected from the ac line to the input supply voltage vcc and a storage capacitor which is connected from vcc to ground. be aware that this capacitor is discharged befor the ic is plugged into the application board. otherwise the ic can be destroyed due to the high capacitor voltage. bootstrap power supply is created with the previous mentioned auxiliary winding and a diode (see application circuit). coolmos the coolmos is designed for very low r dson  to reduce power dissipation.
ICE1PD265G version 1.0 9 10 sep 2001 detin drain leb visense multout ivaout icoil i ovr signal diagrams
iice1pd 265g version 1.0 10 10 sep 2001 absolute maximum ratings parameter symbol min max unit remark supply + zener current icc+iz - 20 ma supply voltage v cc -0.3 vz v vz=zener voltage icc+iz=20ma voltage at pin 2,4,13 -0.3 6.5 v current into pin 3 i vaout -10 30 ma ma vaout=4v,vsense=2.8v vaout=0v,vsense=2.3v t<1ms current into pin 15 i detin -10 10 ma ma detin > 6v detin< 0.4v voltage at pin 6- 11 v drain 650 t j =115c continuous drain current i d 3.2 2 a a t c =25c t c =100c avalanche energy e ar 0.2 mj repetitive esd protection 2000 v mil std 883c method 3015.6, 100pf,1500
ICE1PD265G version 1.0 11 10 sep 2001 characteristics unless otherwise stated, -40c ICE1PD265G version 1.0 12 10 sep 2001 current comparator input bias current i bisense -1 ua input offset voltage v isenseo v isenseo 150 20 mv mv v multin =0v, vaout=2.4v v multin =0v, vaout>2.8v max threshold voltage v isensem 0.95 1.0 1.05 v threshold at ovr v isenovr 0.05 v i ovr =50ua shut down delay t disg 100 ns leading edge blanking t leb 220 ns detector upper threshold voltage v detinu 1.5 v lower threshold voltage v detinl 1v hysteresis v detinhy 0.5 v input current i bdetin -1 ua input clamp voltage high state low state v detinhc v detinlc 5 0.5 i detin =5ma i detin =-5ma multiplier input bias current i bmultin -1 ua dynamic voltage range multin v multin 0 to 4 v v vaout =2.75v dynamic voltage range vaout v vaout v fb to v fb + 1. 5 v multin =1v multiplier gain k low k high 0.18 0.56 v v v vaout <3v v vaout >3.5v restart timer restart time t res 150 us parameter symbol min. typ. max. unit test condition
ICE1PD265G version 1.0 13 10 sep 2001 coolmos drain source breakdown voltage v brdss 600 650 v v t j =25c t j =115c drain source on-resist- ance r dson 1.1 1.4 3.8 ohm ohm t j =25c t j =150c zero gate voltage drain current i dss 0.5 1 70 ua ua u gs =0v, t j =25 u gs =0v, t j =150 output capacitance 1) c oss 150 pf v ds =25v, f=1mhz rise time fall time t rise t fall 30 50 ns ns 1) not tested, guaranteed by design parameter symbol min. typ. max. unit test condition
ICE1PD265G version 1.0 1 4 10 sep 2001 electrical diagrams diagram 1: icc versus vcc 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 0 5 10 15 20 vcc/v icc / ma v cc on v cc off diagram 2: v ccon/off versus temperature 7 8 9 10 11 12 13 14 -40 0 40 80 120 160 tj / c vcc / v v cc on v cc off diagram 4: i ccl versus temperature, v cc =9v 0 5 10 15 20 25 30 35 40 45 50 -40 0 40 80 120 160 tj / c i ccl / ua diagram 3: iccl versus vcc 0 5 10 15 20 25 30 35 40 45 50 0246810121416 vcc / v iccl / ua
ICE1PD265G version 1.0 15 10 sep 2001 diagram 5: v fb vers. temperature (pin1 connected to pin2) 2,45 2,46 2,47 2,48 2,49 2,5 2,51 2,52 2,53 2,54 2,55 -40 0 40 80 120 160 tj / c v fb / v diagram 7: overvoltage regulator v isense vers. threshold voltage 0 0,2 0,4 0,6 0,8 1 1,2 35 37 39 41 43 45 iovp / ua v isense / v v vaout = 3.5v v mu lti n = 3.0v diagram 6: voltage amplifier open loop gain and phase 0 20 40 60 80 100 120 0,01 0,1 1 10 100 1000 10000 f/khz 0 20 40 60 80 100 120 140 160 180 phi/deg g v /db phi g v diagram 8: i ov r versus temperature 35 36 37 38 39 40 41 42 43 44 45 -40 0 40 80 120 160 tj/ c i ovr /ua
ICE1PD265G version 1.0 16 10 sep 2001 diagram 10: leading edge blanking (min on-time) vs. temp. 0 50 100 150 200 250 300 -40 0 40 80 120 160 tj / c leb / ns diagram 12: current sense threshold v isense versus v vaout 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 2,5 3 3,5 4 4,5 v vaout / v v isense / v 1.0 1.5 2.0 3.0 vmultin=4.0 0.5 0.25 diagram 9: max threshold voltage v isensem vs. temperature 0,95 0,96 0,97 0,98 0,99 1 1,01 1,02 1,03 1,04 1,05 -40 0 40 80 120 160 tj/c visensem/v diagram 11: current sense threshold v isense versus v multin 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 01234 v mu l tin / v v isense / v v vaout =2.75v 3.0v 3.25v 3.5v 4.0v 4.5v
ICE1PD265G version 1.0 1 7 10 sep 2001 diagram 13: restart time versus temperature 0 50 100 150 200 250 -40 0 40 80 120 160 tj / c trst / us diagram 14: v brdss vs. temperature 0 100 200 300 400 500 600 700 800 -40 0 40 80 120 160 tj/c vbrdss / v diagram 15: r dso n vs. temperature 0 0,5 1 1,5 2 2,5 3 -40 0 40 80 120 160 tj/c r dson / ohm
ICE1PD265G version 1.0 1 8 10 sep 2001 vin 90-270v ac vout application circuit: r dson =1.1 ohm pout=80w, vin= 180 - 270v ac pout=34w, vin= 90 - 270 v ac c9 100n r9 33k r7 r6 c10 47uf r11 ice1pd265 d5 1n4937 r12 270 r8 100k c4 10n d6 mur115 1234 13 14 15 16 rf filter and rectifier 567 12 11 10 c8 47uf r4 r5 gnd 8 9 r7 5.1k c1 1u c2 1u
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